Характеристики
SN74AHCT125D, ЛП8The SN74AHCT125D is a quadruple Bus Buffer Gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver.
• Inputs are TTL-voltage compatible
• Latch-up performance exceeds 250mA per JESD 17
• Green product and no Sb/Br
Микросхемы / Логические микросхемы / Микросхемы ТТЛ (серия 74)
Корпус: SO14, инфо: Логический элемент ТТЛ буфер с 3 состояниями на выходе КМОП кристалл, примечание: ЛП8