Микросхема SN74ALS138AN

Характеристики

SN74ALS138ANThe SN74ALS138AN is a 3-to-8 Decoder/Demultiplexer designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance systems, these devices can be used to minimize the effects of system decoding. When employed with high-speed memories with a fast enable circuit, the delay times of the decoder and the enable time of the memory are usually less than the typical access time of the memory. The effective system delay introduced by the Schottky-clamped system decoder is negligible. The conditions at the binary-select inputs and the three enable (G1, G2A and G2B) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

• Designed specifically for high-speed memory decoders and data transmission systems
• Incorporate three enable inputs to simplify cascading and/or data reception